(1) Field of the Invention
The present invention relates to a serial parallel type analog to digital converting device having improved accuracy and a simplified multi-stage configuration.
(2) Description of the Prior Art
A conventional analog to digital converting device of the serial parallel type, wherein an output digital signal is formed separately into several groups of bits, consists of several analog to digital converting means, namely, several simple A-D converters, for forming the respective groups of bits, several digital to analog converting means, namely, several simple D-A converters, for converting the several groups of bits to respective equivalent analog signals, several differential amplifiers for obtaining successive differential analog signals between an input analog signal and the respective equivalent analog signals, and another A-D converter for forming a group of the lowest bits, so that, several converting stages are arranged successively in serial parallel.
The serial parallel type analog to digital converting device mentioned above has such a defect that, if an error of signal levels caused by d.c. drift or gain drift of the circuit components comprising any one of the preceding converting stages causes overloading in the following converting stages, high stability and high exactness, namely, high accuracy can not be realized.
To assist in understanding the invention, a serial parallel type analog to digital converting device consisting of two converting stages which form respectively upper 4 bits and lower 4 bits comprising an output digital signal of 8 bits will be explained for example as follows.
In the serial parallel type analog to digital converting device, a preceding converting stage consists of at least an analog to digital (A-D) converter wherein an input analog signal is compared with reference signals, and wherefrom a digital signal is derived as a result of the comparison, a digital to analog (D-A) converter wherein the digital signal is converted to an equivalent analog signal, and a differential amplifier wherefrom a differential output analog signal between the input analog signal and the equivalent analog signal is derived, and a succeeding converting stage consists at least of another A-D converter wherein the differential output analog signal is compared with other reference signals and wherefrom another digital signal is derived as a result of the comparison.
Accordingly, even if circuit components comprising the preceding converting stage have the smallest amount of d.c. drift or gain drift, the drift may cause a large amount of error of the signal levels in the following stage.
In an example of a serial parallel type analog to digital converting device of 8 bits shown in FIG. 1, an input analog signal sample-held by a sample-holder 1 is converted to a digital signal of upper 4 bit by a 4 bits A-D converter 2 in the preceding stage. The 4 bit output digital signal is converted to an equivalent analog signal by a D-A converter 3 in the preceding stage, and then a differential analog signal formed by subtracting the equivalent analog signal from the input analog signal is derived from a differential amplifier 4 in the preceding stage. The differential output analog signal is converted to a digital signal of lower 4 bits by a 4 bit A-D converter 5 in the following stage.
In the converting device shown in FIG. 1, if the differential amplifier 4 has a d.c. drift, an input signal applied to the plus terminal of the differential amplifier 4 from the sample-holder 1, which has applied thereto an input analog signal that is slightly higher than, for instance, the 1/2 level of the normal dynamic range, becomes equivalently lower than the 1/2 level owing to the negative drift of the differential amplifier 4 although the input analog signal is converted to an upper 4 bit digital signal which is higher than the 1/2 level by the upper A-D converter 2. Thus, the level of the differential output analog signal applied to the lower 4 bit A-D converter 5 deviates at the lower side from that of the normal dynamic range of the A-D converter 5, and consequently the A-D converter 5 overloads in the lower direction.
On the contrary, the input analog signal applied to the plus terminal of the differential amplifier 4 from the sample-holder 1, which has applied thereto an input analog signal that is slightly lower than the 1/2 level, becomes equivalently higher than the 1/2 level owing to the positive drift of the differential amplifier 4 although the input analog signal is converted to an upper 4 bit digital signal which is lower than the 1/2 level by the upper A-D converter 2. Thus, the level of the differential output analog signal applied to the lower 4 bit A-D converter 5 deviates at the higher side from that of the normal dynamic range of the A-D converter 5, and consequently the A-D converter 5 overloads in the higher direction.
If the differential amplifier 4 does not have d.c. drift but has a slight amount of gain drift occurring at a signal level which is apart from the d.c. zero level, the result is the same as mentioned above. Further, if the upper A-D converter 2 has inferior accuracy, the result is the same.
As mentioned above, in the serial parallel type analog to digital converting device, if the circuit components comprising the preceding converting stage do not have sufficiently high accuracy, the lower A-D converter 5 in the following converting stage overloads in the upper or lower direction, and consequently an error based on an irregular junction of the output digital signal occurs. Therefore, it is difficult to form a serial parallel type analog to digital converting device having superior accuracy.
One example of a serial parallel type analog to digital converting device wherein the error mentioned above is corrected, is shown in a report of the International Broadcasting Convention held in October, 1974, titled "A Video Analogue to Digital Converter" (pp. 47-57). In the converting device mentioned above, as shown in FIG. 3 on page 51 of the report, the dynamic range of an A-D converter in a following stage is expanded, so as to obviate overloading caused by an input analog signal deviating from the normal dynamic range of the A-D converter owing to an error in a preceding stage. In addition, the range of the output digital signal of the A-D converter, which deviates from the normal dynamic range in response to the input analog signal, is shifted by a uniform level corresponding to the lowest bit of an output digital signal of an A-D converter in the preceding stage, so as to form the same output digital signal as the one corresponding to an input analog signal resting in the normal dyanmic range. Further, a carry signal or a borrow signal is formed in response to the input analog signal deviating from the normal dynamic range in the following stage, and then the carry signal or the borrow signal is respectively added to, or subtracted from the output digital signal of the A-D converter in the preceding stage, so as to correct the error occurring in the preceding stage.
FIG. 2 shows the configuration of the serial parallel type analog to digital converting device having high accuracy improved in the manner mentioned above. A sample-holder 1, a 4 bit A-D converter 2, a 4 bit D-A converter 3 and a differential amplifier 4 in the preceding stage shown in FIG. 2 are the same as those shown in FIG. 1 respectively. On the other hand, a 4 bit A-D converter 6 in the following stage has a dynamic range which is expanded so that it is slightly wider on both sides than a normal one as shown by Table 1 in FIG. 3. Thus, the A-D converter 6 not only converts an input analog signal resting in the normal dynamic range to a 4 bit digital signal, but it can also convert an input analog signal deviating slightly from the normal dynamic range to an equivalent 4 bit digital signal which is the same as an output digital signal corresponding to an input analog signal having a level shifted by just the an amount of the lowest one of the upper 4 bits formed in the preceding stage. The reason is as follows.
For instance, if the level of the input analog signal deviates on the higher side of the normal dynamic range, and then rests in a range which is higher by one step of the upper 4 bits formed in the preceding stage, the upper 4 bits formed in the preceding stage should be corrected by adding one step, which is shown by the lowest one of the upper 4 bit digital signal, and accordingly the lower 4 bits should be shifted by the one step, that is, by the lowest one of the upper 4 bits, so as to correct it in response to the corrected upper 4 bit digital signal.
Furthermore, the A-D converter 6 applies a carry analog signal of "+1" in response to an input signal having a level higher than that of the normal dynamic range, a carry signal of "0" in response to an input analog signal having a level resting in the normal dynamic range, and a borrow signal of "-1" in response to an input analog signal having a level lower than that of the normal dynamic range, to an adder-subtracter 7 respectively, so as to carry or to borrow the 4 bit output digital signal of the A-D converter in the preceding stage.
According to such treatment of the signals as mentioned above, even if the circuit components except the D-A converter 3 and the adder-subtracter 7 in the preceding converting stage have inferior accuracy, the lower 4 bit A-D converter 6 in the following stage never overloads in either direction of the normal dynamic range, and accordingly the irregular junction does not at all occur in the output digital signal. Thus, it is possible to improve the accuracy of the serial parallel type analog to digital converting device.
Nevertheless, in the serial parallel type analog to digital converting device mentioned above, it is required for the A-D converter 6 to form both the carry signal "+1" and the borrow signal "-1" to be applied to the adder-subtracter 7 in response to the level of the input analog signal. Accordingly, it is required that the A-D converter 6 have a complicated circuit configuration, structure, and furthermore it is required that the adder-subtracter 7 use an arithmetical unit capable of both additive and subtractive operations. Therefore, the serial parallel type analog to digital converting device mentioned above has a defect in that its configuration is complicated.